Inductive load power switching circuits

ABSTRACT

Power switching circuits including an inductive load and a switching device are described. The switches devices can be either low-side or high-side switches. Some of the switches are transistors that are able to block voltages or prevent substantial current from flowing through the transistor when voltage is applied across the transistor.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. application Ser. No. 13/959,483, filed Aug. 5, 2013, which is a continuation of U.S. application Ser. No. 13/618,726, filed Sep. 14, 2012 (now U.S. Pat. No. 8,531,232), which is a continuation of U.S. application Ser. No. 12/556,438, filed Sep. 9, 2009 (now U.S. Pat. No. 8,289,065), which claims the benefit of U.S. Provisional Application No. 61/099,451, filed Sep. 23, 2008. The entire disclosure of each of the prior applications is hereby incorporated by reference.

TECHNICAL FIELD

This invention relates to power switching circuits, specifically ones for which an inductive load is used.

BACKGROUND

A single-sided switch is a switching configuration where a switching device is used either to connect the load to a node at a lower potential—a “low-side” switch—or to a node at a higher potential—a “high-side” switch. The low-side configuration is shown in FIG. 1 a, and the high-side configuration is shown in FIG. 2 a, where the node at higher potential is represented by a high voltage (HV) source and the node at lower potential is represented by a ground terminal. In both cases, when the load 10 is an inductive load, a freewheeling diode 11 (sometimes referred to as a flyback diode) is required to provide a path for the freewheeling load current when the switching device is OFF. For example, as seen in FIG. 1 b, when the switching device 12 is biased high by applying a gate-source voltage V_(gs) greater than the device threshold voltage V_(th), current 13 flows through the load 10 and through switching device 12, and diode 11 is reverse biased such that no significant current passes through it. When switching device 12 is switched to low by applying a gate-source voltage V_(gs) <V_(th), as shown in FIG. 1 c, the current passing through the inductive load 10 cannot terminate abruptly, and so current 13 flows through the load 10 and through diode 11, while no significant current flows through switching device 12. Similar diagrams detailing current flow through the high-side switching configuration when the switch is biased high and when the switch is turned off (switched low) are shown in FIGS. 2 b and 2 c, respectively.

Ideally, the freewheeling diodes 11 used in the circuits of FIGS. 1 and 2 have low conduction loss in the ON state as well as good switching characteristics to minimize transient currents during switching, therefore Schottky diodes are commonly used. However, for some applications Schottky diodes cannot support large enough reverse-bias voltages, so high-voltage diodes which exhibit higher conduction and switching losses must be used. Switching devices 12, which are usually transistors, may be enhancement mode (normally off, V_(th)>0), also known as E-mode, or depletion mode (normally on, V_(th)<0), also known as D-mode, devices. In power circuits, enhancement mode devices are typically used to prevent accidental turn on, in order to avoid damage to the devices or other circuit components. A key issue with the circuits in FIGS. 1 and 2 is that most high voltage diodes typically exhibit high conduction and switching loss. Further, reverse recovery currents in high-voltage PIN diodes add to the losses of the transistor.

An alternative to the configurations illustrated in FIGS. 1 and 2 is to instead use synchronous rectification, as illustrated in FIGS. 3 a-e. FIG. 3 a is the same as FIG. 2 a, except that a high-voltage metal-oxide-semiconductor (MOS) transistor 61 is included anti-parallel with diode 11. A standard MOS transistor inherently contains an anti-parallel parasitic diode and can therefore be represented as a transistor 62 anti-parallel to a diode 63, as illustrated in FIG. 3 a. As seen in FIG. 3 b, when switching device 12 is biased high and MOS transistor 61 is biased low, MOS transistor 61 and diode 11 both block a voltage equal to that across the load, so that the entire current 13 flows through the load 10 and through switching device 12. When switching device 12 is switched to low, as shown in FIG. 3 c, diode 11 prevents transistor 62 and parasitic diode 63 from turning on by clamping the gate-drain voltage to a value less than V_(th) of the transistor and less than the turn-on voltage of the parasitic diode. Therefore, almost all of the freewheeling current flows through diode 11, while only a small, insignificant portion flows through the transistor channel and parasitic diode. As shown in FIG. 3 d, MOS device 61 may then be biased high, which results in an increase in the channel conductivity of transistor 62 and thereby cause the majority of the freewheeling current to flow through the transistor channel. However, some dead time must be provided between turn-off of switching device 12 and turn-on of transistor 62 in order to avoid shoot-through currents from the high-voltage supply (HV) to ground. Therefore, diode 11 will be turned on for some time immediately after switching device 12 is switched from high to low and immediately before switching device 12 is switched back from low to high. While this reduces the conduction losses incurred by diode 11 in the absence of MOS transistor 61, the full switching loss for diode 11 is incurred, regardless of how long the diode remains on.

As shown in FIG. 3 e, the circuit in FIGS. 3 a-d can in principle operate without diode 11. In this case, parasitic diode 63 performs the same function that diode 11 performed in the circuit of FIGS. 3 a-d. However, the parasitic diode 63 typically has much poorer switching characteristics and suffers from higher switching losses than a standard high-voltage diode, resulting in increased power loss, so the circuit of FIGS. 3 a-d is usually preferred.

Many power switching circuits contain one or more high-side or low-side switches. One example is the boost-mode power-factor correction circuit shown in FIG. 4 a, which contains a low-side switch. This circuit is used at the input end in AC-to-DC voltage conversion circuits. The configuration for the low-side switch in this circuit is slightly modified from that shown in FIG. 1 a, since in FIG. 1 a the freewheeling diode 11 is connected anti-parallel to the inductive load 10, whereas in this circuit the freewheeling diode 11 is between the inductive load 30 and the output capacitor 35. However, the fundamental operating principles of the two circuits are the same. As seen in FIG. 4 b, when switching device 12 is biased high, current 13 passes through the load 30 and through the switching device 12. The voltage at the cathode end of the freewheeling diode 11 is kept sufficiently high by the output capacitor 35 so that the freewheeling diode 11 is reverse-biased, and thereby does not have any significant current passing through it. As seen in FIG. 4 c, when switching device 12 is switched low, the inductor forces the voltage at the anode of the freewheeling diode 11 to be sufficiently high such that the freewheeling diode 11 is forward biased, and the current 13 then flows through the inductive load 30, the freewheeling diode 11, and the output capacitor 35. Because no significant current can flow in the reverse direction in a diode, diode 11 prevents discharge of the output capacitor 35 through switching device 12 during times where the load current is zero or negative, as can occur if the energy stored in the inductor 30 is completely transferred out before the commencement of the next switching cycle.

SUMMARY

In one aspect, a switch is described that includes a first switching device in series with an assembly comprising a load and a second switching device, the first switching device including a first channel, the second switching device including a second channel, wherein in a first mode of operation the second switching device is capable of blocking a voltage applied across the second switching device in a first direction, in a second mode of operation a substantial current flows through the second channel of the second switching device when a voltage is applied across the second switching device in a second direction and a gate of the second switching device is biased below a threshold voltage of the second switching device, and in a third mode of operation a substantial current flows through the second channel of the second switching device when a voltage is applied across the second switching device in the second direction and the gate of the second switching device is biased above the threshold voltage of the second switching device.

The switch or the assembly can be free of any diodes.

In another aspect, a method of operating a switch is described. At a first time, a gate of a first switching device of a switch is biased higher than a threshold voltage of the first switching device and a gate of a second switching device is biased lower than a threshold voltage of the second switching device, allowing current to flow from a high voltage side of the switch to a low voltage or ground side of the switch through the load. At a second time immediately following the first time, a bias on the gate of the first switching device is changed to be lower than the threshold voltage of the first switching device, causing the second switching device to operate in diode mode and blocking current from flowing to ground. At a third time immediately following the second time, a bias on the gate of the second switching device is changed to be higher than the threshold voltage of the second switching device, wherein changing the bias at the third time reduces conduction loss in comparison to switch operation between the second time and the third time.

In another aspect, a boost-mode power-factor correction circuit is described. The circuit includes a first switching device comprising a first channel, an inductive load, a capacitor, and a second switching device comprising a second channel, wherein the first switching device is connected to a node between the inductive load and a floating gate drive circuit, the second switching device is configured to be connected to the floating gate drive circuit, and the second switching device is between the inductive load and the capacitor.

In yet another aspect, a method of operating the boost-mode power-factor correction circuit is described. The method includes causing a load current through the inductive load to be continuous; at a first time, biasing a gate of the first switching device higher than a threshold voltage of the first switching device and biasing a gate of the second switching device lower than a threshold voltage of the second switching device, allowing current to flow through the first switching device; at a second time immediately following the first time, changing a bias on the gate of the first switching device to be lower than the threshold voltage of the first switching device, causing the first switching device to operate in blocking mode and the second switching device to operate in diode mode, allowing current to flow through the second switching device; at a third time immediately following the second time, changing a bias on the gate of the second switching device to be higher than the threshold voltage of the second switching device, wherein changing the bias at the third time reduces conduction loss in comparison to switch operation between the second time and the third time.

In another aspect, a method of operating the boost-mode power-factor correction circuit is described. The method includes causing a load current through the inductive load to be discontinuous, sensing the load current, and when the load current approaches zero, changing a bias on a gate of the second switching device from a voltage higher than a threshold voltage of the second switching device to a voltage lower than the threshold voltage of the second switching.

In yet another aspect a method of operating the boost-mode power-factor correction circuit is described. The method includes sensing a load current passing through the inductive load, causing the load current to approach zero and immediately increase after approaching zero, and when the load current approaches zero, switching the second switching device from on to off and switching the first switching device from off to on.

In some embodiments, the following features are present. The first mode of operation can comprise biasing the gate of the first switching device above a threshold voltage of the first switching device. The second mode of operation can comprise biasing the gate of the first switching device below a threshold voltage of the first switching device. The first switching device can have a first terminal and a second terminal on opposite sides of the gate, and the first terminal can be adjacent to the assembly and at a higher voltage than the second terminal of the first switching device during operation. The first switching device can have a first terminal and a second terminal on opposite sides of the gate, and the first terminal can be adjacent to the assembly and at a lower voltage than the second terminal of the first switching device during operation. A first node can be between the assembly and the first switching device, a second node can be at a high voltage side of the switch, and the second switching device can be capable of blocking a voltage when voltage at the first node is lower than voltage at the second node. A first node can be between the assembly and the first switching device, a second node can be at a low voltage or ground side of the switch, and the second switching device can be capable of blocking a voltage when voltage at the first node is higher than voltage at the second node. The second switching device can be capable of blocking a same voltage as the first switching device is capable of blocking The second switching device can be capable of blocking voltage in two directions. When the gate of the first switching device is biased lower than a threshold voltage of the first switching device, the second switching device can be capable of conducting current. When the gate of the first switching device is biased lower than the threshold voltage of the first switching device, substantially all current can flow through a single primary channel of the second switching device. When the gate of the second switching device is biased higher than the threshold voltage of the second switching device, the voltage drop across the second switching device can be reduced as compared to when the gate of the second switching device is biased lower than the threshold voltage of the second switching device. The second switching device can have a positive threshold voltage. The first switching device can have a positive threshold voltage. The second switching device can be a HEMT. The second switching device can be a III-Nitride HEMT. The first switching device can be a HEMT. The first switching device can be a III-Nitride HEMT. The second switching device can be structurally the same as the first switching device. A voltage drop across the second switching device can be smaller in the third mode of operation as compared to in the second mode of operation. The load can be an inductive load. The first switching device or the second switching device can comprise a high-voltage depletion mode device and a low-voltage enhancement mode device, the second channel can be a channel of the high-voltage depletion mode device, and the threshold voltage of the second switching device can be a threshold voltage of the low-voltage enhancement mode device. The low-voltage enhancement mode device can at least block a voltage equal to an absolute value of a threshold voltage of the high-voltage depletion mode device. The high-voltage depletion mode device can be a III-Nitride HEMT. The low-voltage enhancement mode device can be a III-Nitride HEMT. The low-voltage enhancement mode device can be a Si MOS device. The device can include a diode connected antiparallel to the low-voltage enhancement mode device. The first switching device can comprise a high-voltage depletion mode device and a low-voltage enhancement mode device, the first channel can be a channel of the high-voltage depletion mode device, and a threshold voltage of the first switching device can be a threshold voltage of the low-voltage enhancement mode device.

Boost-mode power-factor correction circuits can include one or more of the following features. The first switching device can be a III-N HEMT. The second switching device can be a III-N HEMT.

Operating a boost-mode power-factor correction circuit can include causing a load current through the inductive load to be discontinuous, sensing the load current, and when the load current approaches zero, changing a bias on a gate of the second switching device from a voltage higher than a threshold voltage of the second switching device to a voltage lower than the threshold voltage of the second switching device. A load current passing through the inductive load, causing the load current to approach zero and immediately increase after approaching zero is sensed. When the load current approaches zero, the second switching device is switched from on to off and the first switching device is switched from off to on.

Methods described herein may include one or more of the following features or steps. Changing the bias at the third time can reduce conduction loss in comparison to switch operation at the second time.

DESCRIPTION OF DRAWINGS

FIGS. 1 a-c show schematics of a low-side switch, and current paths for various bias conditions.

FIGS. 2 a-c show schematics of a high-side switch, and current paths for various bias conditions.

FIGS. 3 a-e show schematics of high-side switches with a MOSFET connected across the inductive load, and current paths for various bias conditions.

FIGS. 4 a-c show schematics of a boost-mode power-factor correction circuit and current paths for various bias conditions.

FIGS. 5 a-d show schematics of a low-side switch, along with current paths for various bias conditions.

FIG. 5 e shows a biasing scheme for the switching devices in the circuits of FIGS. 5 a-d.

FIGS. 6 a-d show schematics of a high-side switch, along with current paths for various bias conditions.

FIG. 6 e shows a biasing scheme for the switching devices in the circuits of FIGS. 6 a-d.

FIG. 7 shows a schematic of a low-side switch.

FIGS. 8 a-d show schematics of a boost-mode power-factor correction circuit, along with current paths for various bias conditions.

FIG. 8 e shows a biasing scheme for the switching devices in the circuits of FIGS. 8 a-d.

FIGS. 9 a-c show the input current as a function of time for various operating conditions for the circuit in FIG. 8.

DETAILED DESCRIPTION

Low-side and high-side switches and the circuits which they comprise, wherein the freewheeling diode shown in FIGS. 1-3 is replaced by a switching device, such as a transistor, are described below. Embodiments are shown in FIGS. 5 a and 6 a, wherein FIG. 5 a comprises a low-side switch, and FIG. 6 a comprises a high-side switch. In FIGS. 5 a and 6 a, the freewheeling diode used in the circuits of FIGS. 1 and 2 has been replaced by switching device 41. In some embodiments, this device may be the same as the switching device 42 used to modulate the current path. FIGS. 5 b and 6 b illustrate the current path when switching device 42 is biased ON (high) and switching device 41 is biased OFF (low). FIGS. 5 c and 6 c illustrate the current path when switching device 42 is switched OFF. Switching device 41 can be an enhancement mode device, where the threshold voltage V_(th)>0, or a depletion mode device, where the threshold voltage V_(th)<0. In high power applications, it is desirable to use enhancement mode devices with threshold voltages as large as possible, such as V_(th)>2V or V_(th)>3V, a high internal barrier from source to drain at 0 bias (such as 0.5-2 eV), a high ON-to-OFF current ratio (such as >10⁵), along with high breakdown voltage (600/1200 Volts) and low on resistance (<5 or <10 mohm-cm² for 600/1200 V respectively).

Additionally, switching device 41 must have the following characteristics. It must be able to block significant voltage when the voltage at terminal 45/55 is lower than the voltage at terminal 46/56. This condition occurs when switching device 42 is biased high, as shown in FIGS. 5 b and 6 b. As used herein, “blocking a voltage” refers to the ability of a transistor to prevent a current that is greater than 0.0001 times the operating current during regular conduction from flowing through the transistor when a voltage is applied across the transistor. In other words, while a transistor is blocking a voltage which is applied across it, the total current passing through the transistor will not be greater than 0.0001 times the operating current during regular conduction. As used herein, “substantial current” includes any current which is at least ten percent of the operating current during regular conduction. The maximum voltage that switching device 41 must be able to block depends on the particular circuit application, but in general will be the same or very close to the maximum blocking voltage specified for switching device 42. In some embodiments, switching device 41 is able to block voltage in both directions. When switching device 42 is switched OFF, switching device 41 must be capable of conducting current 13 in the direction shown in FIGS. 5 c and 6 c. Furthermore, when the circuit is biased such as shown in FIG. 5 c or 6 c, all substantial current through switching device 41 flows through a single, primary channel of the device, wherein the conductivity of this channel may be modulated by the gate electrode. This is different from the circuits in FIGS. 3 a-3 e, for which applying a voltage signal to the gate electrode of device 61 causes the current to shift from one channel (that of diode 11 or 63) to that of the transistor 62. The maximum current that switching device 41 must be able to conduct in this direction depends on the particular circuit application, but in general will be the same or very close to the maximum current specified for switching device 42. In some embodiments, the switching devices are able to conduct current in both directions.

The detailed operation of the circuit in FIG. 5 is as follows. When switching device 42 is biased ON, such as by setting the gate-source voltage V_(GS42) greater than the device threshold voltage V_(th42), and switching device 41 is biased OFF, such as by setting V_(GS41)<V_(th41), current 13 flows through inductive load 10 and switching device 42, as seen in FIG. 5 b. Here, switching device 41 is said to be in “blocking mode”, as it is supporting a voltage across it while at the same time blocking current from flowing through it, i.e., device 41 is blocking voltage. As shown in FIG. 5 c, when switching device 42 is switched OFF, the current through the inductive load 10 cannot change abruptly, so the voltage at terminal 45 is forced sufficiently high to allow the freewheeling current 13 to be carried through switching device 41. Note that in this mode of operation, current is able to flow through switching device 41 even if V_(GS41) is not changed. This mode of operation for switching device 41 is known as “diode mode operation”. The circuit of FIG. 5 may be preferable to that of FIG. 1 because transistors suitable for use in this application typically have lower conduction and switching losses than diode 11.

Depending on the current level and the threshold voltage of switching device 41, the power dissipation through this device could be unacceptably high when operating in the diode mode. In this case, a lower power mode of operation may be achieved by applying a voltage V_(GS41)>V_(th41) to the gate of switching device 41, as shown in FIG. 5 d. To prevent shoot-through currents from the high-voltage supply (HV) to ground, gate signals of the form shown in FIG. 5 e are applied. The time during which switching device 42 is ON and switching device 41 is OFF is labeled “C” in FIG. 5 e. This corresponds to the mode of operation shown in FIG. 5 b. When switching device 42 is switched OFF, during the time switching device 41 conducts the freewheeling current, the gate of switching device 41 is driven high, allowing the drain-source voltage of switching device 41 to be simply the on-state resistance (Rd_(ds-on)) times the load current. To avoid shoot-through currents from the high-voltage supply (HV) to ground, some dead time must be provided between turn-off of switching device 42 and turn-on of switching device 41. These are the times labeled “A” in FIG. 5 e. During these dead times, switching device 41 operates in the diode mode described above. Since this is a short time in comparison with the entire switching cycle, the relative amount of total power dissipation is low. Time “B” provides the dominant loss factor for switching device 41, and this corresponds to the low-power mode when switching device 41 is fully enhanced. The mode of operation illustrated in FIG. 5 d allows for a further reduction in conduction loss, although switching losses remain unaffected.

In the circuit of FIG. 5, when switching device 42 is switched OFF, all substantial current flows through the primary channel of switching device 41 when the gate of switching device 41 remains low (FIG. 5 c) as well as when it is driven high (FIG. 5 d). This may be preferable to the operation of the circuit in FIG. 3, for which substantial current initially flows through a diode while transistor 61 remains low and only flows through the primary transistor channel once the gate of transistor 61 is driven high. Diode 11 and parasitic diode 63 in FIG. 3 typically exhibit higher switching losses than transistors 41 suitable for use in the circuit of FIG. 5. Additionally, switching devices 41 and 42 in FIG. 5 can be identical or similar devices, which simplifies the fabrication of this circuit.

The detailed operation of the circuit in FIG. 6 is similar to that of FIG. 5. When switching device 42 is biased ON, such as by setting V_(GS42)>V_(th42), and switching device 41 is biased OFF, such as by setting V_(GS41)<V_(th41), current 13 flows through inductive load 10 and switching device 42, as seen in FIG. 6 b. As shown in FIG. 6 c, when switching device 42 is switched OFF, the current through the inductive load 10 cannot change abruptly, so the voltage at terminal 56 is forced sufficiently negative to allow the freewheeling current 13 to be carried through switching device 41, and switching device 41 now operates in diode mode. Again, in this mode of operation, current is able to flow through switching device 41 even if V_(GS41) is not changed. As with the circuit of FIG. 5, power dissipation during diode mode operation of switching device 41 may be reduced by applying a voltage V_(GS41)>V_(th41) to the gate of switching device 41, as shown in FIG. 6 d. Again, some dead time must be provided between turn-off of switching device 42 and turn-on of switching device 41 in order to avoid shoot-through currents from the high-voltage supply (HV) to ground, and so the bias scheme shown in FIG. 6 e is used.

Examples of devices that meet the criteria specified above for switching device 41 are metal-semiconductor field effect transistors (MESFETs) of any material system, junction field effect transistors (JFETs) of any material system, high electron mobility transistors (HEMTs or HFETs) of any material system, including vertical devices such as current aperture vertical electron transistors (CAVETs), and bidirectional switches comprised of the devices listed above, such as those described U.S. application Ser. No. 12/209,581, filed Sep. 12, 2008, which is hereby incorporated by reference throughout. Common material systems for HEMTs and MESFETs include Ga_(x)Al_(y)In_(1-x-y)N_(m)As_(n)P_(1-m-a) or III-V materials, such as III-N materials, III-As materials, and III-P materials. Common materials for JFETs include III-V materials, SiC, and Si.

Preferably, switching device 41 is an enhancement mode device to prevent accidental turn on, in order to avoid damage to the device or other circuit components. III-Nitride (III-N) devices, such as III-Nitride HFETs, are especially desirable due to the large blocking voltages that can be achieved with these devices. The device preferably also exhibits a high access region conductivity (such as sheet resistance<750 ohms/square) along with high breakdown voltage (600/1200 Volts) and low on resistance (<5 or <10 mohm-cm² for 600/1200 V respectively). The device can also include any of the following: a surface passivation layer, such as SiN, a field plate, such as a slant field plate, and an insulator underneath the gate. In other embodiments, switching device 41 is a SiC JFET.

A variation on switching device 41, which can be used with any of the embodiments described herein, embodiment is shown in FIG. 7. In this embodiment, switching device 41 includes a high-voltage depletion mode (D-mode) device 97 connected to a low-voltage enhancement mode (E-mode) device 96 as shown. This configuration for switching device 41 operates similarly to the case when a high-voltage E-mode device is used for switching device 41. When the voltage at node 46 is higher than that at node 45 and the gate of E-mode device 96 is biased at 0V or below the threshold voltage of E-mode device 96, D-mode device 97 blocks the voltage across the switch. This configuration can be advantageous because high-voltage E-mode devices are typically difficult to fabricate. The D-mode device 97 is capable of blocking the maximum voltage drop across the switch, which for high-voltage applications can be 600V or 1200V or other suitable blocking voltage required by the application. Typical D-mode device threshold voltages for high-voltage devices are about −5 to −10V (D-mode=negative V_(th)). The E-mode device 96 can block at least |V_(th)|, where |V_(th)| is the magnitude (absolute value) of the threshold voltage of the D-mode device. In some embodiments the E-mode device can block about 2*|V_(th)|. In some embodiments, the D-mode device can block about 1200V and has a threshold voltage of about −5V, and the E-mode device blocks at least about 5V, such as at least about 10V. D-mode device 97 can be a high-voltage III-N HEMT device, and E-mode device 96 can be a Si MOS device or a III-N HEMT device. When a Si MOS device is used for device 96, diode 99, which is a low-loss diode such as Schottky diode, can optionally be connected antiparallel to device 96, as shown, in order to reduce switching losses by preventing turn-on of the parasitic reverse diode inherent in Si MOSFETs. A similar configuration to the one shown for switching device 41 in FIG. 7 can also be used for switching device 42, and the configuration may also be used for switching devices 41 and 42 in the high-side switch of FIG. 6. More details of the operation of this configuration can be found in U.S. application Ser. No. 12/209,581.

A boost-mode power-factor correction circuit is shown in FIG. 8 a. This circuit is similar to that shown in FIG. 4 a, except that diode 11 has been replaced by a switching device 41 connected to a floating gate-drive circuit 72. Switching device 41 must meet the same specifications as switching device 41 in FIGS. 5 and 6. The details of operation of this circuit are as follows. When switching device 42 is biased ON and switching device 41 is biased OFF, as seen in FIG. 8 b, current 13 passes through the load 30 and through the switching device 42. The voltage at node 77 is kept sufficiently high by the output capacitor 35 so that switching device 41 is in blocking mode, and thereby does not have any substantial current passing through it. As seen in FIG. 8 c, when switching device 42 is switched OFF, the inductor forces the voltage at node 76 to be sufficiently high such that switching device 41 switches to diode mode, and the current 13 then flows through the inductive load 30, switching device 41, and the output capacitor 35.

As with the circuits in FIGS. 5 and 6, conduction losses in this circuit can be reduced by applying a voltage V_(GS41)>V_(th41) to the gate of switching device 41, as shown in FIG. 8 d. However, for this circuit to operate properly, the timing of the signals applied by gate-drive circuit 72 to the gate of switching device 41 must be properly controlled. There are three cases which need to be considered independently. The first, illustrated in FIG. 9 a, is the case where the load current is continuous (continuous mode). The second, illustrated is FIG. 9 b, is the case where the load current is discontinuous (discontinuous mode), such that no current flows during some portion of the duty cycle. For this second case, it is also possible that the load current is negative (flows in the opposite direction through the load) during some portion of the duty cycle. This may occur if there are any inductive or capacitive components leading into the input of this circuit. The third, illustrated in FIG. 9 c, is the case where the load current approaches zero but then immediately increases again. This mode is known as the “critical mode”.

If the load current is continuous, then the timing of the gate signals to switching devices 42 and 41 is similar to that of the circuits in FIGS. 5 and 6. To allow the load current to flow through switching device 42, switching device 42 is switched ON and switching device 41 is switched OFF, as in FIG. 8 b. When switching device 42 is switched OFF, the inductor forces the load current through switching device 41 as shown in FIG. 8 c, and switching device 41 is in diode mode. While current flows through switching device 41, conduction losses can be reduced by applying a voltage V_(GS41)>V_(th41) to the gate of switching device 41, as shown in FIG. 8 d. Some dead time must be provided between turn-off of switching device 42 and turn-on of switching device 41 in order to prevent the capacitor 35 from discharging through switching devices 42 and 41, and so the bias scheme shown in FIG. 8 e is used.

The current in the inductor can become discontinuous or negative if the energy stored in it is completely transferred, either to the output capacitor or through switching device 42, before the commencement of the next switching cycle. In circuits where the switching device 41, or flyback transistor, is connected in parallel to the load, such as those in FIGS. 5 and 6, there is no harm in leaving the flyback transistor enhanced even after the load current has dropped to zero. However, in the power factor correction circuit of FIG. 8, where the flyback transistor is between inductor 30 and capacitor 35, incorrect operation would result from leaving switching device 41 enhanced after the load current drops to zero, because the current would reverse sign and start discharging the output capacitor. In such a system, the load current must be sensed, either directly or indirectly, and if switching device 41 is on, it must be turned off when the current approaches zero. For example, switching device 41 can be turned off once the current has dropped to 0.1%, 1%, 3%, or 5% of the peak current.

The third case, the critical mode, is essentially the same as the discontinuous mode, with the difference that the switching device 42 turns back on as soon as the load current approaches zero. This implies that the switching frequency is not fixed, but adjustable, as in a hysteretic controller. The control circuit is therefore very different from the discontinuous case, but the requirement regarding the switching sequence of the switching devices 42 and 41 is the same. The current must be sensed to know when it has approached zero, and switching device 41 must be turned off when the current approaches zero. 

What is claimed is:
 1. A power-factor correction circuit, comprising: a first switching device; an inductive load; a capacitor; and a second switching device, the second switching device comprising a depletion mode device and an enhancement mode device, the enhancement mode device including a gate, the depletion mode device including a channel; wherein the first switching device is connected to a node between the inductive load and the second switching device, and the second switching device is between the inductive load and the capacitor.
 2. The power-factor correction circuit of claim 1, wherein the circuit is configured such that in a first mode of operation current flows through the channel of the depletion mode device in a first direction when the gate of the enhancement mode device is biased below a threshold voltage of the enhancement mode device, and in a second mode of operation current flows through the channel of the depletion mode device in the first direction when the gate of the enhancement mode device is biased above the threshold voltage of the enhancement mode device.
 3. The power-factor correction circuit of claim 2, wherein the circuit is configured such that in a third mode of operation the depletion mode device blocks voltage applied in a second direction across the switching device.
 4. The power-factor correction circuit of claim 3, wherein in the third mode of operation the enhancement mode device blocks a voltage at least equal to an absolute value of a threshold voltage of the depletion mode device.
 5. The power-factor correction circuit of claim 3, wherein in the third mode of operation the gate of the enhancement mode device is biased below the threshold voltage of the enhancement mode device.
 6. The power-factor correction circuit of claim 1, wherein the depletion mode device is a high-voltage device, the enhancement mode device is a low-voltage device, and the second switching device is configured to operate as a high-voltage enhancement mode device.
 7. The power-factor correction circuit of claim 1, wherein the depletion mode device comprises a III-N HEMT.
 8. The power-factor correction circuit of claim 7, wherein the enhancement mode device comprises a Si MOS device or a III-N HEMT.
 9. The power-factor correction circuit of claim 7, wherein the enhancement mode device comprises a Si MOS device, the Si MOS device includes an inherent parasitic diode, and the switching device further comprises a Schottky diode connected antiparallel to the Si MOS device.
 10. A power-factor correction circuit, comprising: a first switching device comprising a first depletion mode transistor and a first enhancement mode transistor; a second switching device comprising a second depletion mode transistor and a second enhancement mode transistor; an inductive component; and a capacitor; wherein the first switching device and the second switching device are connected to a first node, and the second switching device and the capacitor are connected to a second node.
 11. The power-factor correction circuit of claim 10, wherein the inductive component is connected to the first node.
 12. The power-factor correction circuit of claim 11, wherein the first and second depletion mode transistors each comprise III-N HEMTs.
 13. The power-factor correction circuit of claim 12, wherein the first and second enhancement mode transistors each comprise Si MOS devices.
 14. The power-factor correction circuit of claim 12, wherein the circuit is configured such that in a first mode of operation current flows through a channel of the second depletion mode transistor in a first direction when a gate of the second enhancement mode transistor is biased below a threshold voltage of the second enhancement mode transistor, and in a second mode of operation current flows through the channel of the second depletion mode transistor in the first direction when the gate of the second enhancement mode transistor is biased above the threshold voltage of the second enhancement mode transistor.
 15. The power-factor correction circuit of claim 14, wherein the circuit is configured such that in a third mode of operation the second depletion mode transistor blocks voltage applied in a second direction across the second switching device.
 16. The power-factor correction circuit of claim 15, wherein in the third mode of operation the second enhancement mode transistor blocks a voltage at least equal to an absolute value of a threshold voltage of the second depletion mode transistor.
 17. The power-factor correction circuit of claim 15, wherein in the third mode of operation the gate of the second enhancement mode transistor is biased below the threshold voltage of the second enhancement mode transistor.
 18. A method of forming a power-factor correction circuit, comprising: providing a first switching device, an inductive load, a capacitor, and a second switching device, the second switching device comprising a depletion mode device and an enhancement mode device, the enhancement mode device including a gate, the depletion mode device including a channel; and connecting the first switching device to a node between the inductive load and the second switching device, wherein the second switching device is between the inductive load and the capacitor.
 19. The method of claim 18, wherein the circuit is configured such that in a first mode of operation current flows through the channel of the depletion mode device in a first direction when the gate of the enhancement mode device is biased below a threshold voltage of the enhancement mode device, and in a second mode of operation current flows through the channel of the depletion mode device in the first direction when the gate of the enhancement mode device is biased above the threshold voltage of the enhancement mode device.
 20. The method of claim 19, wherein the circuit is configured such that in a third mode of operation the depletion mode device blocks voltage applied in a second direction across the switching device.
 21. The method of claim 20, wherein in the third mode of operation the enhancement mode device blocks a voltage at least equal to an absolute value of a threshold voltage of the depletion mode device.
 22. The method of claim 20, wherein in the third mode of operation the gate of the enhancement mode device is biased below the threshold voltage of the enhancement mode device.
 23. The method of claim 18, wherein the depletion mode device is provided as a high-voltage device, the enhancement mode device is provided as a low-voltage device, and the second switching device is configured to operate as a high-voltage enhancement mode device.
 24. The method of claim 18, wherein the depletion mode device comprises a III-N HEMT.
 25. The method of claim 24, wherein the enhancement mode device comprises a Si MOS device or a III-N HEMT.
 26. The method of claim 24, wherein the enhancement mode device comprises a Si MOS device, the Si MOS device includes an inherent parasitic diode, and the switching device further comprises a Schottky diode connected antiparallel to the Si MOS device.
 27. A method of forming a power-factor correction circuit, comprising: providing a first switching device comprising a first depletion mode transistor and a first enhancement mode transistor; providing a second switching device comprising a second depletion mode transistor and a second enhancement mode transistor; providing an inductive component; providing a capacitor; and connecting the first switching device and the second switching device to a first node, and connecting the second switching device and the capacitor to a second node.
 28. The method of claim 27, further comprising connecting the inductive component to the first node.
 29. The method of claim 28, wherein the first and second depletion mode transistors each comprise III-N HEMTs.
 30. The method of claim 29, wherein the first and second enhancement mode transistors each comprise Si MOS devices.
 31. The method of claim 29, wherein the circuit is configured such that in a first mode of operation current flows through a channel of the second depletion mode transistor in a first direction when a gate of the second enhancement mode transistor is biased below a threshold voltage of the second enhancement mode transistor, and in a second mode of operation current flows through the channel of the second depletion mode transistor in the first direction when the gate of the second enhancement mode transistor is biased above the threshold voltage of the second enhancement mode transistor.
 32. The method of claim 31, wherein the circuit is configured such that in a third mode of operation the second depletion mode transistor blocks voltage applied in a second direction across the second switching device.
 33. The method of claim 32, wherein in the third mode of operation the second enhancement mode transistor blocks a voltage at least equal to an absolute value of a threshold voltage of the second depletion mode transistor.
 34. The method of claim 32, wherein in the third mode of operation the gate of the second enhancement mode transistor is biased below the threshold voltage of the second enhancement mode transistor. 